The application claims the benefit of U.S. Provisional application No. 60/275,745.
The present invention relates to fabricating an integrated circuit, containing interconnecting lines with vertical connectors of vias, and, more specifically, to fabricating interconnecting lines with ultra small vias.
The fabrication of integrated circuits devices are well known and are manufactured by fabricating a plurality of transistors, such as field effect transistors (FET) and passive devices on and in a semiconductor substrate, such as silicon. In the case of an FET, a gate material, such as polysilicon, is disposed over a relatively thin gate insulator, such as silicon oxide on and in a semiconductor substrate. The gate material and gate insulator are patterned to form gate conductors, and impurities are deposited adjacent to and on opposite sides of the gate conductors to dope the gate material and to form source/drain regions of either N-type or P-type depending on the type of impurity. If the impurity is N-type, then the resulting FET is an NMOS with an N-channel and, if the impurity is a p-type, then the resulting FET is a PMOS with a P-channel. In addition, if the device contains both an NMOS and a PMOS, the device is a CMOS.
With the increased need to fabricate more complex and higher levels of integrated circuits with faster transistors, such as FETs, it has become necessary to reduce the dimensions of the interconnections between the transistors and especially the vertical connections or vias between the connecting lines.
However, a reduction in the physical dimensions of the connectors or vias between the connection lines is limited by conventional photolithographic techniques used to define the hole for the vertical connector. Photolithography is used to pattern a photoresist, which is disposed above an insulating material. Silicon oxide typically is used as the insulating material to separate the conductive lines. An optical image is transferred to and exposes the photoresist by projecting radiation, normally deep ultraviolet light through the transparent portions of a mask plate containing the layout and dimensions of the holes for the vertical connectors. Depending on whether the photoresist is positive or negative, the solubility of the exposed photoresist is either increased or decreased by a photochemical reaction. The photoresist is developed by dissolving the resist areas of higher solubility with a solvent, leaving a mask pattern on the insulating material, such as silicon oxide. This mask pattern protects the underlying insulating material during etching of the material to define the shape and dimension of the vertical conductor or via in the insulating layer of the integrated circuit.
Thus, the overlying photoresist pattern defines the dimensions of vertical holes or vias in the insulating material. The minimum dimension that can be achieved for a patterned photoresist is limited by the resolution of the optical system used to project the image onto the photoresist.
Therefore, it would be desirable to develop a fabrication method in which the physical dimensions of holes or vias in insulating material can be made smaller while still using a conventional photolithographic system.
Accordingly, it is an object of the present invention to provide a method of fabricating an integrated circuit with a hole or via which uses a photolithographic system but employs a technique to achieve smaller dimensions.
Another object of the present invention is to provide a method of fabricating an integrated circuit with ultra small holes or vias with minimal modification to the photolithographic system.
A semiconductor material, such as a silicon wafer, is fabricated with a very large number of transistors, such as FETs, and, if desired, passive elements. An insulating layer is disposed over the transistors and passive elements. A photoresist layer is disposed on the insulating layer, and the resist is first exposed to a conventional deep ultra violet light pattern and then exposed to the same light pattern but with the pattern and wafer rotated ninety degrees (90xc2x0) relative to each other and the two pattern exposures overlapping each other. Each exposure dose is not sufficient to develop the non-overlapped resist exposure pattern but is sufficient to develop the smaller overlapped exposure pattern.